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19-1587; Rev 0; 11/99
Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface
General Description
The MAX5104 low-power, serial, voltage-output, dual 12-bit digital-to-analog converter (DAC) consumes only 500A from a single +5V supply. This device features Rail-to-Rail(R) output swing and is available in a spacesaving 16-pin QSOP package. To maximize the dynamic range, the DAC output amplifiers are configured with an internal gain of +2V/V. The 3-wire serial interface is SPITM/QSPITM/MICROWIRETM compatible. Each DAC has a double-buffered input organized as an input register followed by a DAC register, which allows the input and DAC registers to be updated independently or simultaneously with a 16-bit serial word. Additional features include programmable powerdown (2A), hardware power-down lockout (PDL), a separate reference voltage input for each DAC that accepts AC and DC signals, and an active-low clear input (CL) that resets all registers and DACs to zero. These devices provide a programmable logic pin for added functionality, and a serial-data output pin for daisy chaining.
____________________________Features
o 12-Bit Dual DAC with Internal Gain of +2V/V o Rail-to-Rail Output Swing o 12s Settling Time o +5V Single-Supply Operation o Low Quiescent Current 500A (normal operation) 2A (power-down mode) o SPI/QSPI/MICROWIRE Compatible o Space-Saving 16-Pin QSOP Package o Power-On Reset Clears Registers and DACs to Zero o Adjustable Output Offset
MAX5104
Ordering Information
PART MAX5104CEE MAX5104EEE TEMP. RANGE 0C to +70C -40C to +85C PINPACKAGE 16 QSOP 16 QSOP INL (LSB) 4 4
________________________Applications
Industrial Process Control Remote Industrial Controls Digital Offset and Gain Adjustment Microprocessor-Controlled Systems Motion Control Automatic Test Equipment (ATE)
Pin Configuration appears at end of data sheet.
Functional Diagram
DOUT CL PDL DGND AGND VDD REFA OSA DECODE CONTROL R
R INPUT REG A DAC REG A DAC A R OUTA OSB
16-BIT SHIFT REGISTER SR CONTROL
MAX5104
LOGIC OUTPUT SCLK UPOH INPUT REG B DAC REG B DAC B
R OUTB
CS
DIN
REFB
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
1
________________________________________________________________ Maxim Integrated Products
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769.
Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface MAX5104
ABSOLUTE MAXIMUM RATINGS
VDD to AGND............................................................-0.3V to +6V VDD to DGND ...........................................................-0.3V to +6V AGND to DGND ..................................................................0.3V OSA, OSB to AGND.......................(VAGND - 4V) to (VDD + 0.3V) REF_, OUT_ to AGND.................................-0.3V to (VDD + 0.3V) Digital Inputs (SCLK, DIN, CS, CL, PDL) to DGND ...........................................(-0.3V to +6V) Digital Outputs (DOUT, UPO) to DGND .....-0.3V to (VDD + 0.3V) Maximum Current into Any Pin .........................................20mA Continuous Power Dissipation (TA = +70C) 16-Pin QSOP (derate 8.30mW/C above +70C).......667mW Operating Temperature Ranges MAX5104CEE ...................................................0C to +70C MAX5104EEE.................................................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V 10%, VREFA = VREFB = +2.048V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C (OS_ connected to AGND for a gain of +2V/V).) PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Offset Tempco Gain Error Gain-Error Tempco VDD Power-Supply Rejection Ratio REFERENCE INPUT Reference Input Range Reference Input Resistance REF RREF Minimum with code 1554 hex Input code = 1FFE hex, VREF_ = 0.67Vp-p at 2.5VDC Input code = 0000 hex, VREF_ = (VDD - 1.4Vp-p), f = 1kHz SINAD Input code = 1FFE hex, VREF_ = 1Vp-p at 1.25VDC, f = 25kHz CL, PDL, CS, DIN, SCLK CL, PDL, CS, DIN, SCLK 200 VIN = 0 to VDD 0.001 8 1 3 0.8 0 14 20 VDD - 1.4 V k PSRR Normalized to 2.048V 4.5V VDD 5.5V INL DNL VOS TCVOS (Note 1) Guaranteed monotonic Code = 10 Normalized to 2.048V 4 -0.2 4 20 600 8 12 4 1 10 Bits LSB LSB mV ppm/C LSB ppm/C V/V SYMBOL CONDITIONS MIN TYP MAX UNITS
MULTIPLYING-MODE PERFORMANCE Reference 3dB Bandwidth Reference Feedthrough Signal-to-Noise plus Distortion Ratio DIGITAL INPUTS Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance VIH VIL VHYS IIN CIN V V mV A pF 300 -82 75 kHz dB dB
2
_______________________________________________________________________________________
Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V 10%, VREFA = VREFB = +2.048V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C (OS_ connected to AGND for a gain of +2V/V).) PARAMETER Output High Voltage Output Low Voltage DYNAMIC PERFORMANCE Voltage Output Slew Rate Output Settling Time Output Voltage Swing OSA or OSB Input Resistance Time Required to Exit Shutdown Digital Feedthrough Digital Crosstalk POWER SUPPLIES Positive Supply Voltage Power-Supply Current Power-Supply Current in Shutdown Reference Current in Shutdown TIMING CHARACTERISTICS SCLK Clock Period SCLK Pulse Width High SCLK Pulse Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time SDI Setup Time SDI Hold Time SCLK Rise to DOUT Valid Propagation Delay SCLK Fall to DOUT Valid Propagation Delay SCLK Rise to CS Fall Delay CS Rise to SCLK Rise Hold CS Pulse Width High tCP tCH tCL tCSS tCSH tDS tDH tDO1 tDO2 tCS0 tCS1 tCSW CLOAD = 200pF CLOAD = 200pF 10 40 100 (Note 4) 100 40 40 40 0 40 0 80 80 ns ns ns ns ns ns ns ns ns ns ns ns VDD IDD (Note 3) 4.5 0.5 2 0 5.5 0.65 10 1 V mA A A CS = VDD, SCLK = 100kHz, VSCLK = 5Vp-p ROS_ SR To 1/2LSB of full-scale, VSTEP = 4V Rail-to-rail (Note 2) 24 0.75 15 0 to VDD 34 25 5 5 V/s s V k s nVs nVs SYMBOL VOH VOL ISOURCE = 2mA ISINK = 2mA CONDITIONS MIN VDD - 0.5 0.13 0.40 TYP MAX UNITS V V DIGITAL OUTPUTS (DOUT, UPO)
MAX5104
IDD(SHDN) (Note 3)
Note 1: Accuracy is specified from code 6 to code 4095. Note 2: Accuracy is better than 1LSB for VOUT_ greater than 6mV and less than VDD - 50mV. Guaranteed by PSRR test at the end points. Note 3: Digital inputs are set to either VDD or DGND, code = 0000 hex, RL = . Note 4: SCLK minimum clock period includes the rise and fall times.
_______________________________________________________________________________________
3
Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface MAX5104
__________________________________________Typical Operating Characteristics
(VDD = +5V, RL = 10k, CL = 100pF, OS_ pins connected to AGND, TA = +25C, unless otherwise noted.)
REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE
MAX5104 toc01
SUPPLY CURRENT vs. TEMPERATURE
MAX5104 toc02
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
VREF = +1Vp-p AT 2.5VDC CODE = 1FFE (HEX) -40 THD + N (dB)
MAX5104 toc03
0 -2 -4 RELATIVE OUTPUT (dB) -6 -8 -10 -12 -14 -16 -18 -20 1 370 740 1110 1480 VREF = +0.67Vp-p AT 2.5VDC CODE = 1FFE (HEX)
700 650 SUPPLY CURRENT (A) 600 550 500 450 400 VREF = +2.048V RL = -55 -35 -15 5 25 45 65 CODE = 0000 (HEX) CODE = 1FFE (HEX)
-30
-50
-60
-70
-80 1 10 FREQUENCY (kHz) 100
1850
85 105 125
FREQUENCY (kHz)
TEMPERATURE (C)
FULL-SCALE ERROR vs. RESISTIVE LOAD
MAX5104 toc04
REFERENCE FEEDTHROUGH AT 1kHz
-60 -70 RELATIVE OUTPUT (dB) -80 -90 -100 -110 -120 -130 VREF = +3.6Vp-p AT 1.88VDC CODE = 0000 (HEX)
MAX5104 toc05
0.50 VREF = +2.048V 0.25 FULL-SCALE ERROR (LSB) 0 -0.25 -0.50 -0.75 -1.00 -1.25 -1.50 0.1 1 RL (k) 10
-50
-140 -150 100 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FREQUENCY (kHz)
SHUTDOWN CURRENT vs. TEMPERATURE
VREF = +1V 5 SHUTDOWN CURRENT (A) 4 3 2 1 0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
MAX5104 toc06
OUTPUT FFT PLOT
-10 -20 RELATIVE OUTPUT (dB) -30 -40 -50 -60 -70 -80 -90 -100 0.5 1.6 2.7 3.8 4.9 6.0 FREQUENCY (kHz) NOTE: RELATIVE TO FULL SCALE VREF = +2.45Vp-p AT 1.225VDC f = 1kHz CODE = 1FFE (HEX)
MAX5104 toc07
6
0
4
_______________________________________________________________________________________
Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface
_____________________________Typical Operating Characteristics (continued)
(VDD = +5V, RL = 10k, CL = 100pF, OS_ pins connected to AGND, TA = +25C, unless otherwise noted.)
MAX5104
DYNAMIC RESPONSE RISE TIME
MAX5104 toc08
DYNAMIC RESPONSE FALL TIME
MAX5104 toc09
CS 5V/div
CS 5V/div
OUT_ 1V/div
OUT_ 1V/div
2s/div VREF = +2.048V VREF = +2.048V
2s/div
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX51504 toc10
MAJOR-CARRY TRANSITION
MAX5104 toc11
0.60 CODE = 1FFE (HEX) SUPPLY CURRENT (mA) 0.55
CS 2V/div 0.50 CODE = OOOO (HEX) 0.45 OUT_ 50mV/div AC-COUPLED
0.40 4.50 4.75 5.00 5.25 5.50 5s/div TRANSITION FROM 1000 (HEX) TO 0FFE (HEX) SUPPLY VOLTAGE (V)
ANALOG CROSSTALK
MAX5104 toc12
DIGITAL FEEDTHROUGH
MAX5104 toc13
OUTA 5V/div
SCLK 5V/div
OUTB 200V/div AC-COUPLED
OUTA 500V/div AC-COUPLED
250s/div VREF = +2.048V, GAIN = +2V/V, CODE = 1FFE HEX
2.5s/div
_______________________________________________________________________________________
5
Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface MAX5104
_____________________Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME AGND OUTA OSA REFA CL CS DIN SCLK DGND DOUT UPO PDL REFB OSB OUTB VDD FUNCTION Analog Ground
R R OS_
DAC A Output Voltage DAC A Offset Adjustment Reference for DAC A Active-Low Clear Input. Resets all registers to zero. DAC outputs go to 0V. Chip-Select Input Serial-Data Input Serial-Clock Input Digital Ground Serial-Data Output User-Programmable Output Power-Down Lockout. The device cannot be powered down when PDL is low. Reference for DAC B DAC B Offset Adjustment DAC B Output Voltage Positive Power Supply
REF_ AGND 2R 2R
R
R
R
OUT_
2R D10
2R D11
2R D12
D0
Figure 1. Simplified DAC Circuit Diagram
VOUT = (VREF * NB / 4096) * 2 where NB is the numeric value of the DAC's binary input code (0 to 4095) and VREF is the reference voltage. The reference input impedance ranges from 14k (1554 hex) to several gigohms (with an input code of 0000 hex). The reference input capacitance is code dependent and typically ranges from 15pF with an input code of all zeros to 50pF with a full-scale input code.
Output Amplifier
The MAX5104's output amplifiers have internal resistors that provide for a gain of +2V/V when OS_ is connected to AGND. These resistors are trimmed to minimize gain error. The output amplifiers have a typical slew rate of 0.75V/s and settle to 1/2LSB within 15s, with a load of 10k in parallel with 100pF. Loads less than 2k degrade performance. The OS_ pin can be used to produce an adjustable offset voltage at the output. For instance, to achieve a 1V offset, apply -1V to the OS_ pin to produce an output range from 1V to (1V + VREF * 2). Note that the DAC's output range is still limited by the maximum output voltage specification.
_______________Detailed Description
The MAX5104 dual, 12-bit, voltage-output DAC is easily configured with a 3-wire serial interface. The device includes a 16-bit data-in/data-out shift register, and each DAC has a double-buffered input composed of an input register and a DAC register (see Functional Diagram). In addition, trimmed internal resistors produce an internal gain of +2V/V that maximizes output voltage swing. The amplifier's offset-adjust pin allows for a DC shift in the DAC's output. Both DACs use an inverted R-2R ladder network that produces a weighted voltage proportional to the input voltage value. Each DAC has its own reference input to facilitate independent full-scale values. Figure 1 depicts a simplified circuit diagram of one of the two DACs.
Power-Down Mode
The MAX5104 features a software-programmable shutdown mode that reduces the typical supply current to 2A. The two DACs can be powered down independently, or simultaneously using the appropriate programming command. Enter power-down mode by writing the appropriate input-control word (Table 1). In power-down mode, the reference inputs and amplifier outputs become high impedance, and the serial interface remains active. Data in the input registers is saved,
Reference Inputs
The reference inputs accept both AC and DC values with a voltage range extending from 0 to (VDD - 1.4V). Determine the output voltage using the following equation (OS_ = AGND):
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Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface
Table 1. Serial-Interface Programming Commands
16-BIT SERIAL WORD A0 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 C1 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 C0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 D11.......................D0 (MSB) (LSB) 12-bit DAC data 12-bit DAC data 12-bit DAC data 12-bit DAC data 12-bit DAC data XXXXXXXXXXXX XXXXXXXXXXXX 0 0 1 X XXXXXXXX 1 0 1 X XXXXXXXX 1 1 0 X XXXXXXXX 1 1 1 X XXXXXXXX 0 1 0 X XXXXXXXX 0 1 1 X XXXXXXXX 1 0 0 1 XXXXXXXX 1 0 0 0 XXXXXXXX 0 0 0 X XXXXXXXX FUNCTION S0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Load input register A; DAC registers are unchanged. Load input register B; DAC registers are unchanged. Load input register A; all DAC registers are updated. Load input register B; all DAC registers are updated. Load all DAC registers from the shift register (start up both DACs with new data). Update both DAC registers from their respective input registers (start up both DACs with data previously stored in the input registers). Shut down both DACs (provided PDL = 1). Update DAC register A from input register A (start up DAC A with data previously stored in input register A). Update DAC register B from input register B (start up DAC B with data previously stored in input register B). Power Down DAC A (provided PDL = 1). Power Down DAC B (provided PDL = 1). UPO goes low (default). UPO goes high. Mode 1, DOUT clocked out on SCLK's rising edge. Mode 0, DOUT clocked out on SCLK's falling edge (default). No operation (NOP).
MAX5104
X = Don't care Note: D11, D10, D9, and D8 become control bits when A0, C1, and C0 = 0. S0 is a sub-bit, always zero.
allowing the MAX5104 to recall the output state prior to entering power-down when returning to normal mode. Exit power-down by recalling the previous condition or by updating the DAC with new information. When returning to normal operation (exiting power-down), wait 20s for output stabilization.
SCLK
SK
Serial Interface
The MAX5104's 3-wire serial interface is compatible with both MICROWIRE (Figure 2) and SPI/QSPI (Figure 3) serial-interface standards. The 16-bit serial input word consists of 1 address bit, 2 control bits, 12 bits of data (MSB to LSB), and 1 sub-bit as shown in Figure 4. The address and control bits determine the MAX5104's response, as outlined in Table 1.
MAX5104
DIN
SO
MICROWIRE PORT
CS
I/O
Figure 2. Connections for MICROWIRE
7
_______________________________________________________________________________________
Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface
+5V
SS
DIN
MOSI SPI/QSPI PORT
MAX5104
SCLK
SCK
The MAX5104's digital inputs are double buffered, which allows any of the following: loading the input register(s) without updating the DAC register(s), updating the DAC register(s) from the input register(s), or updating the input and DAC registers concurrently. The address and control bits allow the DACs to act independently. Send the 16-bit data as one 16-bit word (QSPI) or two 8-bit packets (SPI, MICROWIRE), with CS low during this period. The address and control bits determine which register will be updated, and the state of the registers when exiting power-down. The 3-bit address/control determines the following: * Registers to be updated * Clock edge on which data is to be clocked out via the serial-data output (DOUT) * State of the user-programmable logic output * Configuration of the device after power-down The general timing diagram of Figure 5 illustrates how data is acquired. Driving CS low enables the device to receive data; otherwise, the interface control circuitry is disabled. With CS low, data at DIN is clocked into the register on the rising edge of SCLK. As CS goes high, data is latched into the input and/or DAC registers, depending on the address and control bits. The maximum clock frequency guaranteed for proper operation is 10MHz. Figure 6 shows a more detailed timing diagram of the serial interface.
MAX5104
CS
I/O
CPOL = 0, CPHA = 0
Figure 3. Connections for SPI/QSPI
MSB...................................................................................LSB 16 Bits of Serial Data Address Bits A0 Control Bits C1, C0 MSB...Data Bits...LSB D11.......................D0 12 Data Bits Sub Bit S0 0
1 Address/2 Control Bits
Figure 4. Serial-Data Format
CS COMMAND EXECUTED SCLK 1 DIN A0 C1 C0 D11 D10 D9 D8 8 D7 D6 9 D5 D4 D3 D2 D1 D0 16 S0
Figure 5. Serial-Interface Timing Diagram
8
_______________________________________________________________________________________
Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface MAX5104
CS tCSO SCLK tDS DIN tDH tCSS tCL tCH tCP tCSH tCS1 tCSW
Figure 6. Detailed Serial-Interface Timing Diagram
SCLK
SCLK
SCLK
MAX5104
DIN CS DOUT DIN CS
MAX5104
DOUT DIN CS
MAX5104
DOUT
TO OTHER SERIAL DEVICES
Figure 7. Daisy Chaining MAX5104s
DIN SCLK CS1 CS2 CS3 TO OTHER SERIAL DEVICES
CS
CS
CS
MAX5104
SCLK DIN
MAX5104
SCLK DIN
MAX5104
SCLK DIN
Figure 8. Multiple MAX5104s Sharing a Common DIN Line
_______________________________________________________________________________________ 9
Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface MAX5104
Serial-Data Output
The serial-data output, DOUT, is the internal shift register's output. DOUT allows for daisy chaining of devices and data readback. The MAX5104 can be programmed to shift data out of DOUT on SCLK's falling edge (Mode 0) or on the rising edge (Mode 1). Mode 0 provides a lag of 16 clock cycles, which maintains compatibility with SPI/QSPI and MICROWIRE interfaces. In Mode 1, the output data lags 15.5 clock cycles. On power-up, the device defaults to Mode 0.
+5V/+3V REF_ VDD R OS_
MAX5104
R DAC_ AGND GAIN = +2V/V DGND OUT_
User-Programmable Logic Output
User-programmable logic output (UPO) allows an external device to be controlled through the serial interface (Table 1), thereby reducing the number of microcontroller I/O pins required. On power-up, UPO is low.
Figure 9. Unipolar Output Circuit (Rail-to-Rail)
+5V/+3V REF_ VDD VOS R OS_
Power-Down Lockout Input
The power-down lockout (PDL) pin disables software shutdown when low. When in power-down, transitioning PDL from high to low wakes up the part with the output set to the state prior to power-down. PDL can also be used to asynchronously wake up the device.
MAX5104
Daisy-Chaining Devices
Any number of MAX5104s can be daisy-chained by connecting the DOUT pin of one device to the DIN pin of the following device in the chain (Figure 7). Since the MAX5104's DOUT pin has an internal active pull-up, the DOUT sink/source capability determines the time required to discharge/charge a capacitive load. See the digital output VOH and VOL specifications in the Electrical Characteristics. Figure 8 shows an alternate method of connecting several MAX5104s. In this configuration, the data bus is common to all devices; data is not shifted through a daisy chain. More I/O lines are required in this configuration because a dedicated chip-select input (CS) is required for each IC.
DAC _ AGND
R OUT_ DGND
Figure 10. Setting OS_ for Output Offset
Table 2. Unipolar Code Table (Gain = +2)
DAC CONTENTS MSB LSB 1 1 1 1 1 1 1 1 11 1 1 ( 0 ) ANALOG OUTPUT
4095 +VREF 2 4096 2049 +VREF 2 4096 2048 +VREF 4096
__________Applications Information
Unipolar Output
Figure 9 shows the MAX5104 configured for unipolar, rail-to-rail operation with a gain of +2V/V. The MAX5104 can produce a 0 to 4.096V output with a 2.048V reference (Figure 9). Table 2 lists the unipolar output codes. An offset to the output can be achieved by connecting a voltage to OS_, as shown in Figure 10. By applying VOS_ = -1V, the output values will range between 1V and (1V + VREF * 2).
1 0 0 0 0 0 0 0 00 0 1 ( 0 )
1 0 0 0 0 0 0 0 00 0 0 ( 0 )
2 =
VREF
0 1 1 1 1 1 1 1 11 1 1 ( 0 )
2047 +VREF 2 4096 1 +VREF 2 4096
0000 0000 0001 (0) 0 0 0 0 0 0 0 0 00 0 0 ( 0 )
Bipolar Output
The MAX5104 can be configured for a bipolar output (Figure 11). The output voltage is given by the equation (OS_ = AGND):
10
0V
Note: ( ) are for the sub-bit.
______________________________________________________________________________________
Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface
VOUT = VREF [((2 * NB) / 4096) - 1] where NB represents the numeric value of the DAC's binary input code. Table 3 shows digital codes and the corresponding output voltage for Figure 11's circuit.
Harmonic Distortion and Noise
The total harmonic distortion plus noise (THD+N) is typically less than -78dB at full scale with a 1Vp-p input swing at 5kHz.
MAX5104 MAX5104
Using an AC Reference
In applications where the reference has an AC signal component, the MAX5104 has multiplying capabilities within the reference input voltage range specifications. Figure 12 shows a technique for applying a sinusoidal input to REF_, where the AC signal is offset before being applied to the reference input.
Digital Calibration and Threshold Selection
Figure 13 shows the MAX5104 in a digital calibration application. With a bright-light value applied to the photodiode (on), the DAC is digitally ramped until it trips the comparator. The microprocessor (P) stores this "high" calibration value. Repeat the process with a dim light (off) to obtain the dark current calibration.
Table 3. Bipolar Code Table
DAC CONTENTS MSB LSB 1111 1111 1 111 (0) ANALOG OUTPUT
2047 2048
+5V/ +3V +5V/+3V 26k AC REFERENCE INPUT
+VREF
MAX495
1000 0000 0 001 (0) 1000 0000 0 000 (0) 0111 1111 1 111 (0)
1 +VREF 2048
500mVp-p
10k
REF
VDD
R
OS_
0V
R
1 -VREF 2048 2047 +VREF 2 4096 -VREF 2048 = - VREF 2048
DAC_
OUT_
0000 0000 0 001 (0)
MAX5104
AGND DGND
0000 0000 0 000 (0)
Note: ( ) are for the sub-bit.
Figure 12. AC Reference Input Circuit
V+
REF_
+5V/+3V
10k OS_
10k
REF_
+5V/+3V OS_ VDD R
PHOTODIODE
VDD R
MAX5104
R DAC _ DGND AGND OUT_ 10k 10k
V+
MAX5104
VOUT P DIN DAC _ AGND DGND R OUT_
V+ VOUT VRPULLDOWN
V-
Figure 11. Bipolar Output Circuit
Figure 13. Digital Calibration
11
______________________________________________________________________________________
Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface MAX5104
VDD OSA
MAX5104
VIN REFA CS SCLK DIN VREF REFB SHIFT REGISTER INPUT REG A INPUT REG B DAC REG A DAC REG B
R
R OUTA DACA
R1 R2
DACB R R
OUTB
R3 R4
VOUT
VOUT = GAIN - OFFSET OSB
IN
[ ][ ] = (V 2NA )( R2 )(1+ R4 ) (V [ 4096 R1+R2 R3 ] [
REF
2NB 4096
)( R4 )] R3
AGND
DGND
NA IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACA. NB IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACB.
Figure 14. Digital Control of Gain and Offset
The P then programs the DAC to set an output voltage at the midpoint of the two calibrated values. Applications include tachometers, motion sensing, automatic readers, and liquid-clarity analysis.
Pin Configuration
TOP VIEW
AGND 1 OUTA 2 OSA 3 REFA 4 CL 5 CS 6 DIN 7 SCLK 8 16 VDD 15 OUTB 14 OSB
Digital Control of Gain and Offset
The two DACs can be used to control the offset and gain for curve-fitting nonlinear functions, such as transducer linearization or analog compression/expansion applications. The input signal is used as the reference for the gain-adjust DAC, whose output is summed with the output from the offset-adjust DAC. The relative weight of each DAC output is adjusted by R1, R2, R3, and R4 (Figure 14).
MAX5104
13 REFB 12 PDL 11 UPO 10 DOUT 9 DGND
Power-Supply Considerations
On power-up, the input and DAC registers clear (set to zero code). For rated performance, VREF_ should be at least 1.4V below VDD. Bypass the power supply with a 4.7F capacitor in parallel with a 0.1F capacitor to AGND. Minimize lead lengths to reduce lead inductance.
QSOP
Chip Information
TRANSISTOR COUNT: 3053 SUBSTRATE CONNECTED TO AGND
Grounding and Layout Considerations
Digital and AC transient signals on AGND can create noise at the output. Connect AGND to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane. Carefully lay out the traces between channels to reduce AC cross-coupling and crosstalk. Wire-wrapped boards and sockets are not recommended. If noise becomes an issue, shielding may be required.
Package Information
Package information is available on Maxim's website: www.maxim-ic.com.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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